As semiconductor memory technology continues to advance and the size of memory cells continues to shrink, problems associated with bridges formed during the manufacturing process between neighboring memory cells (e.g., due to manufacturing defects such as conductive particles) become more pronounced. Such bridges create resistive shorts between neighboring memory cells that can cause the memory device to malfunction. Severe ridges between neighboring memory cells can be detected during testing of memory devices and addressed, for example, using row and/or column redundancy techniques. However, if the bridge results in a more resistive short, detection of such bridge during the wafer or package test becomes more difficult. Often, such undetected bridges result in premature failure of the part in the field.
A number of techniques for detecting bridges have been proposed. However, all these techniques require complex test algorithms and/or extensive on-chip circuitry which lengthen the test time and/or increase the die size. Thus, there is a need for a simple detection technique that can successfully detect even small leakages due to bridges between adjacent cells using simple circuitry and without increasing the test time.